1. Field of the Invention
The present invention relates to a capacitor using a ferroelectric film employed in an FeRAM (Ferroelectric Random Access Memory), and particularly to a method of manufacturing a parallel plate capacitor.
2. Description of the Related Art
As has been shown in a prior art document, a capacitor of an FeRAM device generally has a horizontal-type parallel plate structure and comprises a lower electrode, a ferroelectric film and an upper electrode. A method of forming the upper electrode, the ferroelectric film and the lower electrode by batch-processing, using the same mask has been carried out extensively because of the merit of micro precision (see Japanese Unexamined Patent Publication No. 2003-243621).
Although a vertical-type parallel plate capacitor has also been known, the application thereof to a ferroelectric capacitor had not been carried out because its manufacturing method was difficult (see Japanese Unexamined Patent Publication No. Hei 6(1994)-77430 and No. 2002-299555).
The prior art will be explained below. A device isolation oxide film 2, a gate electrode 3 and a source-drain diffused layer 4 are formed in a silicon substrate 1. Thereafter, an interlayer insulating film 5 such as a silicon oxide film is deposited over the silicon substrate 1 and contact regions 6 are made open.
Then, a tungsten (W) film is deposited by a CVD method or the like and planarized to thereby form contacts 6 with tungsten embedded therein. Further, a first platinum (Pt) film 7 having a thickness of 150 nm, which serves as a lower electrode, an SBT (SrBi2Ta2O9) film 8 having a thickness of 150 nm corresponding to a ferroelectric, and a second platinum film 9 having a thickness of 150 nm, which serves as an upper electrode, are sequentially formed (see FIG. 1).
A resist pattern 10 is formed by the normal photolithography technique, and the second platinum film 9 that serves as the upper electrode, the ferroelectric SBT film 8 and the first platinum film 7 that serves as the lower electrode are collectively etched (see FIG. 2). Although not shown in the drawing, a resist pattern 10 is removed in a manner similar to the prior art and an interlayer insulating film is formed over the entire surface. Thereafter, wirings for connecting a gate electrode 3, a source-drain diffused layer 4, a contact 6, etc. are formed to obtain a conventional ferroelectric capacitor.
In the prior art, a noble metal such as platinum, iridium (Ir) or the like is generally used for a lower electrode and an upper electrode. Since these metals are poor in chemical reactivity, their processing is generally based on an ion milling method corresponding to physical etching without depending on a chemical one.
Thus, a problem arose in that as shown in FIG. 3 corresponding to an enlarged view of a capacitor section, the side face of a ferroelectric capacitor was subjected to an etching gas and ions 11 upon batch etching of the ferroelectric capacitor, thereby sustaining plasma damage 12, so that a ferroelectric film 8 at a capacitor outer peripheral portion was deteriorated in quality and a sufficient function was not obtained as a memory. The batch etching could not be done in order to prevent the plasma damage 12 of the ferroelectric film 8 (see Japanese Unexamined Patent Publication Nos. 2000-228494 and 2000-228494).
A problem also arose in that when a contact section 14 was made open on an upper electrode 9 as shown in FIG. 4, a ferroelectric capacitor was subjected to an etching gas and ions, so that a charge-up electrical charge caused plasma damage to a ferroelectric film 8.